ECE 380 - Ultimate Study Guide Flashcards
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| 2188742264 | Multiplexer | (a.k.a. mux) A gate that, using an additional input, selects one of several analog or digital input signals and forwards the selected input into a single (output) line. | 0 | |
| 2200762968 | demultiplexer | the opposite of a multiplexer: a gate that forwards its single input onto a selected one of several analog or digital output signals. Decoder circuits can be used as demultiplexers. | 1 | |
| 2188742265 | Adder | A digital circuit that performs the addition of numbers. | 2 | |
| 2188742266 | Half-adder | A basic adder, composed of two inputs, two outputs (sum and carry-out), an AND gate and an XOR gate. | 3 | |
| 2188751330 | Carry-out | In addition, one of two outputs created- here, the one carried into the addition of the next, more significant bit. | 4 | |
| 2228861904 | Full-adder | An adder that takes in three inputs (including, generally, a previous carry-out) and produces two outputs. Can be constructed either out of two connected half-adders and an OR gate, or a 3-input XOR gate, and 3 AND gates acting as the input for a 3-input OR gate. | 5 | |
| 2188751329 | Ripple-Carry Adder | An adder constructed from several parallel full-adders, each feeding its "carry" output into the adder of the left bit. Unlike the carry-lookahead adder, is simpler to implement but does not do anything to determine the carries to be calculated prior to finding answer. | 6 | |
| 2228850498 | Carry-lookahead Adder | Unlike the Ripple-Carry adder, has the advantage of calculating one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. It does this by modifying its full-adders and implementing a structure called a carry lookahead, which handles only the processing of carry-outs. Instead of each full adder returning just s, "sum," and c, "carry," and feeding its carry to the next full-adder, each here computes s as well as - p, "propagate" (x OR y) - g, "generate" (x AND y) These two are passed to the carry lookahead to be evaluated. If both are false, there is no carry-out to the next bit. The value of the resulting carry, which is still limited to 0 or 1, is equal to c_i = g + (p*c_i-1) = (x AND y) OR ((x OR y) AND c_i-1) A typical and simple n-bit carry-lookahead adder is implemented with four common gates per bit (two options: 2 XORs/1 OR/1 AND; or 1 XOR/2 ORs/1 AND), plus a number of AND gates equal to the number of bits so far- so five gates for the first digit, six more for the second digit, seven gates for the third, et cetera. | 7 | |
| 2188751333 | Signed Numbers | Numbers that can be positive or negative, as opposed to unsigned numbers, which are always positive. In most binary conventions, the rightmost (n-1) digits of a signed number represent its range of potential unsigned magnitudes. | 8 | |
| 2188760880 | Flip-flop | (a.k.a. latch) A logic circuit for storage. Has two stable states and can be used to store state information. Equivalent to a bit of memory. The multiple-bit equivalent is called a "register." (Likely not to be featured on the test.) | 9 | |
| 2199859824 | MSB/LSB | Most significant bit- the bit representing the greatest order of magnitude in a number: typically the leftmost for unsigned numbers, and the one immediately to the right of it for signed numbers. Least significant bit- the bit representing the lowest order of magnitude in a number: typically the rightmost bit. | 10 | |
| 2199699561 | Sign-and-magnitude | The "familiar" method of signing numbers: prefacing the value with a boolean value indicating whether it is negative. In digital logic, this scheme is represented by implementing an additional bit prior to the magnitude of the number- one that is false (0) if the number is positive and true (1) if the number is negative. Example: Should we use four bits (three unsigned) to represent signed numbers: +5 = 0101; -5 = 1101 +3 = 0011; -3 = 1011 | 11 | |
| 2199729985 | complementary number system | An alternative to the sign-and-magnitude system, considered more practical and efficient for most digital mathematical operations. Negative numbers are defined according to a subtraction operation involving positive numbers. | 12 | |
| 2199692008 | 1's complement | The more basic complementary number system. Easy to derive (just take the complement of each bit), but comes with drawbacks when used in arithmetic operations. In this, an n-bit negative number (K₁) is obtained by subtracting its equivalent positive number (P) from 2ⁿ - 1; so K₁ = (2ⁿ - 1) - P. Example: Using four bits (three unsigned) once again: -5 = 1111-0101 = 1010 -3 = 1111-0011 = 1100 | 13 | |
| 2199692009 | 2's complement | Necessary for stable subtraction! In this, an n-bit negative number (K₂) is obtained by subtracting its equivalent positive number (P) from 2ⁿ; so K₂= (2ⁿ) - P. Negative numbers are equal to their 1's complement representation plus one. Example: Using four bits (three unsigned) once again: -5 = 10000-0101 = 1011 -5 = 10000-0o11 = 1101 | 14 | |
| 2199792554 | radix | The base of a counting system. Binary is radix-2. Octal is radix-8. Decimal is radix-10. Hexadecimal is radix-16. | 15 | |
| 2199816853 | 1's Complement Addition | Often straightforward (simply add the values normally and interpret the result as a 1's complement), although sometimes this produces a carry-out in the form of an additional leftmost digit- when this happens, the carry-out must be added to the least significant bit. This correction can double the time of the process. (+5)0101 / / / / (-5)1010 (+2)0010 / / / (+2)0010 _______ / / /_______ (+7)0111 / / / /(-3)1100 (+5)0101 (-2)1101 _______ 10010 => add leftmost digit to rightmost digit (+3)0011 <=|| | 16 | |
| 2199879097 | 2's Complement Addition/Subtraction | Addition is formed by direct addition of the numbers. Like with 1's complement, may produce an extra digit- but in this case, can be ignored. Subtraction is, thus, most effective in this form from a physical standpoint- it's done by simply taking the 2's complement of the subtrahend and adding it to the minuend. (+5)0101 / / / / (-5)1011 (+2)0010 / / / (+2)0010 _______ / / /_______ (+7)0111 / / / /(-3)1101 (+5)0101 (-2) 1110 _______ 10011 => ignore new digit (+3)0011 <=|| | 17 | |
| 2199896631 | subtrahend/minuend | Refer to the number to be subtracted, and the number from which the subtrahend is subtracted, respectedly. In short: Minuend - subtrahend = Product | 18 | |
| 2200447355 | digital multiplication | 19 | ||
| 2200456470 | decoders and encoders | Circuits used (of course) to decode and encode information. A binary decoder decodes information from n inputs into an output of 2ⁿ bits. A binary encoder encodes information from 2ⁿ inputs into an n-bit code. This likely won't be on the test. | 20 | |
| 2228835312 | How to do binary multiplication by hand | Technically "technically" identical to decimal multiplication by hand: you multiply the entirety of one factor by the digits of the other, adding the resulting products together. As shifting the entirety of a number one digit to the left in the decimal system multiplies its value by 10, doing so in the binary system multiplies it by 2. | 21 | |
| 2229113809 | Positive logic vs Negative logic | Refers to the respective conventions of representing high voltage levels (V_DD) and low voltage levels (Gnd) as 1 and 0 (Positive logic), or 0 and 1 (Negative logic), respectively. | 22 | |
| 2228841363 | PMOS | Positive-channel metal-oxide semiconductors. A type of MOSFET transistor. Operates as a switch- when the input signal is low, the switch opens (turns off) and when the input signal is high, the switch closes (turns on). Passes 1 well, and 0, poorly. | 23 | |
| 2228841364 | NMOS | Negative-channel metal-oxide semiconductors. A type of MOSFET transistor. Operates as a switch- when the input signal is low, the switch closes (turns on) and when the input signal is high, the switch opens (turns off). Passes 0 well, and 1, poorly. | 24 | |
| 2228841783 | CMOS | A circuit logic system using PMOS and NMOS transistors- the "C" stands for "complementary." | 25 | |
| 2229168614 | Transmission gates | An NMOS transistor and a PMOS transistor, combined into a single switch with an input x, an output f and a selector input, s, working in conjunction with its complement, ~s. ~s is connected to the p-channel transistor, while s is connected to the n-channel transistor- when s is low, the transistors open, turning the switch off; when s is high, the transistors close, turning the switch on and making f=x. These have a variety of applications, not the least of which are to efficiently implement XOR gates and multiplexers. | 26 | |
| 2228943652 | NMOS transistor counts for logic gates | Note: "i" here refers to the fan-in of the gate. NOT gates: 1 NMOS transistor can invert a signal (1) NAND/NOR gates: 1 transistor per input (i) AND/OR gates: Like their inverted counterparts, with an transistors for inversion (i + 1) In addition to the given number of transistors, NMOS logic gates must also implement a pull-up device, usually in the form of a resistor. | 27 | |
| 2228872759 | CMOS transistor counts for logic gates | Note: "i" here refers to the fan-in of the gate. NOT gates: One NMOS, one PMOS (2) NAND/NOR gates: 2 transistors per input (2i) AND/OR gates: Like their inverted counterparts, with 2 extra transistors for inversion (2i + 2) 2-input XOR gate: Two transmission gates, two inverters- all one NMOS, one PMOS. (8) 2-part multiplexer: Two transmission gates, one inverter. (6) Here, an NMOS circuit continues to act as a Pull-Down Network while the introduced PMOS circuit acts as a Pull-Up Network. In typical implementations, the structure of the PMOS network complements the NMOS in every way; for example, if two given inputs connect to parallel transistors in the PDN, they'll connect to sequential transistors in the PUN, and vice-versa. | 28 | |
| 2228899002 | MOSFET transistors | Operate as basic switches with either positive or negative logic, turning on and off depending on the amount of current run through them. Consist of four main parts: The SOURCE and DRAIN are two physically identical terminals that The GATE acts as the "location" of voltage V(G) The SUBSTRATE (or body) is connected to the electrical ground (Gnd). | 29 | |
| 2229678199 | fan-in, fan-out | Fan-in refers to the number of inputs to a specific gate. The number of other gates a specific gate drives is called its fan-out. | 30 | |
| 2461111420 | Setup time | (t[su]) The amount of time a data signal must remain stable in a storage circuit PRIOR TO reaching a pertinent ("trigger") clock edge AVERAGE SETUP TIME: t[su][avg] = .3 ns | 31 | |
| 2461111421 | Hold time | (t[h]) The amount of time a data signal must remain stable in a storage circuit AFTER reaching a pertinent ("trigger") clock edge AVERAGE HOLD TIME: t[h][avg] = .2 ns | 32 | |
| 2461118603 | Clock-to-Q propagation delay | (t[cQ]) | 33 | |
| 2461133964 | basic latch | AKA S-R latch AKA Set-Reset latch. One of the most basic circuits for storage. Basically "remembers" whether its value was recently SET to 1 or RESET to 0. | 34 | |
| 2461139869 | gated D latch | Prefaced with enable gates, | 35 | |
| 2461141534 | D flip-flop | Essentially two D-latches, connected and receiving complementary clock signals. | 36 | |
| 2461149444 | T flip-flop | A "toggle" flip-flop- "inverts" when E (enable) = T (data) = 1. | 37 | |
| 2461151834 | JK flip-flop | 38 | ||
| 2461153275 | Synchronous transmission | Synchronous transmissions are synchronized by an external clock. ADVANTAGES: - Simple, doesn't require synchronization of both communication sides - Cheap, because asynchronous transmission requires less hardware - Setup is faster than other transmissions, so well suited for applications where messages are generated at irregular intervals, for example data entry from the keyboard, and the speed depends on different applications. DISADVANTAGE: - Large relative overhead, a high proportion of the transmitted bits are uniquely for control purposes and thus carry no useful information | 39 | |
| 2461154023 | Asynchronous transmission | Asynchronous transmissions are synchronized by special signals along the transmission medium (here, usu. ultimately connected to the same sort of clock). ADVANTAGE: - Lower overhead and thus, greater throughput DISADVANTAGE: - Slightly more complex and thus, more expensive | 40 |
